Patent · US Active

Gate-all-around integrated circuit structures having fin stack isolation

US11594637B2 · kind B2 · utility

0Cited by

3References

13Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Leonard P. GULER · Hillsboro, US
Stephen D. Snyder · Portland, US
Biswajeet Guha · Hillsboro, US
William Hsu · Hillsboro, US
Urusa Alaan · Hillsboro, US
Tahir Ghani · Portland, US
Michael K. Harper · Hillsboro, US
Vivek Thirtha · Portland, US
Shu Zhou · Portland, US
Nitesh Kumar · Pune, IN

Key dates

Filing date	Mar 27, 2020
Grant date	Feb 28, 2023
Priority date	—
Expiry date	Apr 5, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/017
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.