Stackable fully molded semiconductor structure with through silicon via (TSV) vertical interconnects
US11616003B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2022 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Jun 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/1058
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may include an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device. Encapsulant may be disposed over at least five sides of the embedded device. A first electrical interconnect structure may be coupled to a first end of the TSV at the first surface of the embedded device, and a second electrical interconnect structure may be coupled to a second end of the TSV at the second surface of the embedded device. A semiconductor die (e.g. a system on chip (SoC), memory device, microprocessor, graphics processor, or analog device), may be mounted over the first electrical interconnect of the TSV.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.