Method for making semiconductor device with selective etching of superlattice to define etch stop layer
US11631584B1 · kind B1 · utility
7Cited by
123References
20Claims
0Family size
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Key dates
| Filing date | Oct 28, 2021 |
| Grant date | Apr 18, 2023 |
| Priority date | — |
| Expiry date | Oct 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a semiconductor device may include forming a superlattice above a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include selectively etching the superlattice to remove semiconductor atoms and cause non-semiconductor atoms to accumulate and define an etch stop layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.