Ingaas epi structure and wet etch process for enabling III-v GAA in art trench

US11631737B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Sanaz K. Gardner · Portland, US
• Willy Rachmady · Beaverton, US
• Matthew V. Metz · Portland, US
• Gilbert Dewey · Beaverton, US
• Jack T. Kavalieros · Portland, US
• Chandra S. Mohapatra · Hillsboro, US
• Anand S. Murthy · Beaverton, US
• Nadia M. Rahhal-Orabi · Hillsboro, US
• Nancy Zelick · Portland, US
• Tahir Ghani · Portland, US

Key dates

• Filing date: Dec 24, 2014
• Grant date: Apr 18, 2023
• Expiry date: Dec 24, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.