Method for manufacturing semiconductor structure with buried power line and buried signal line
US11647623B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2021 |
| Grant date | May 9, 2023 |
| Priority date | — |
| Expiry date | Jan 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for manufacturing a semiconductor structure. The method includes providing a substrate having a first top surface; forming an isolation region in the substrate to surround an active region; forming a recess in the active region; disposing a first conductive material within the recess to form a buried power line and a buried signal line; forming a first circuit layer and a second circuit layer on the first top surface of the substrate, wherein the first circuit layer covers the buried power line and the buried signal line, and the second circuit layer is separated from the first circuit layer; and forming a cell capacitor over the first circuit layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.