Patent · US Active

Wafer testing and structures for wafer testing

US11650249B1 · kind B1 · utility

1Cited by
3References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 28, 2020
Grant dateMay 16, 2023
Priority date—
Expiry dateMay 21, 2041

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/2884
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

Examples described herein generally relate to wafer testing and structures implemented on a wafer for wafer testing. In an example method for testing a wafer, power is applied to a first pad in a test site (TS) region on the wafer. The TS region is electrically connected to a device under test (DUT) region on the wafer. The DUT region includes a DUT. The TS region and DUT region are in a first and second scribe line, respectively, on the wafer. A third scribe line is disposed on the wafer between the TS region and the DUT region. A signal is detected from a second pad in the TS region on the wafer. The signal is at least in part a response of the DUT to the power applied to the first pad.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.