Field effect transistor with enhanced reliability
US11658234B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2021 |
| Grant date | May 23, 2023 |
| Priority date | — |
| Expiry date | Jun 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/411
Abstract
A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, a source contact and a drain contact on the barrier layer, an insulating layer on the semiconductor layer between the source contact and the drain contact, and a gate contact on the insulating layer. The gate contact includes a central portion that extends through the insulating layer and contacts the barrier layer and a drain side wing that extends laterally from the central portion of the gate toward the drain contact by a distance ΓD. The drain side wing of the gate contact is spaced apart from the barrier layer by a distance d1 that is equal to a thickness of the insulating layer. The distance ΓD is less than about 0.3 μm, and the distance d1 is less than about 80 nm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.