Systolic arithmetic on sparse data

US11663746B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Abhishek R. Appu · Cameron Park, US
• Prasoonkumar Surti · Folsom, US
• Jill MacDonald Boyce · Manalapan, US
• Subramaniam Maiyuran · Citrus, US
• Michael Apodaca · Folsom, US
• Adam T. Lake · Portland, US
• James M. Holland · Folsom, US
• Vasanth Ranganathan · Cameron Park, US
• Altug Koker · Cameron Park, US
• Lidong Xu · Beijing, CN
• Nikos Kaburlasos · Lincoln, US

Key dates

• Filing date: Nov 11, 2020
• Grant date: May 30, 2023
• Expiry date: Mar 17, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G06N3/084
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides hardware logic to apply a numerical transform to matrix data to increase the sparsity of the data. Increasing the sparsity may result in a higher compression ratio when the matrix data is compressed.