In-memory computation device and in-memory computation method to perform multiplication operation in memory cell array according to bit orders
US11664070B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2021 |
| Grant date | May 30, 2023 |
| Priority date | — |
| Expiry date | Jul 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An in-memory computation device and computation method are provided. The in-memory computation device, including a memory cell array, an input buffer, and a sense amplifier, is provided. The memory cell array includes a memory cell block. The memory cell block corresponds to at least one word line, and stores multiple weight values. Memory cells on the memory cell block respectively store multiple bits of each weight value. The input buffer is coupled to multiple bit lines, and respectively transmits multiple input signals to the bit lines. The memory cell array performs a multiply-add operation on the input signals and the weight values to generate multiple first operation results corresponding to multiple bit orders. The sense amplifier adds the first operation results to generate a second operation result according to the bit orders corresponding to the first operation results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.