Column redundancy techniques
US11664086B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2021 |
| Grant date | May 30, 2023 |
| Priority date | — |
| Expiry date | Jul 14, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein are directed to a device having memory architecture with an array of memory cells arranged in multiple columns with redundancy including first columns of memory cells disposed in a first region along with second columns of memory cells and redundancy columns of memory cells disposed in a second region that is laterally opposite the first region. The device may have column shifting logic that is configured to receive data from the multiple columns, shift the data from the first columns in the first region to a first set of the redundancy columns in the second region, and shift data from the second columns in the second region to a second set of the redundancy columns in the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.