Patent · US Active

Multi-step high aspect ratio vertical interconnect and method of making the same

US11664321B2 · kind B2 · utility

0Cited by

1References

19Claims

0Family size

Assignee

Deca Technologies USA, Inc. · US

Inventors

Clifford Sandstrom · Richfield, US
Craig Bishop · Scottsdale, US
Timothy L. Olson · Phoenix, US

Key dates

Filing date	Feb 1, 2022
Grant date	May 30, 2023
Priority date	—
Expiry date	Feb 1, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2224/96
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A multi-step conductive interconnect (MSI) may comprise a first step of the MSI comprising a first end and a second end opposite the first end, a first height (Ha) and a first diameter (Da). A second step of the MSI may comprise a first end and a second end opposite the first end. The first end of the second step contacts the second end of the first step. The second step may comprise a second height (Hb) and a second diameter (Db). The MSI may comprise a height (H) and a height to width aspect ratio (H:Da) greater than or equal to 1.5:1. A sidewall of the first step may comprise an offset (O) with respect to a sidewall of the second step to form a disjointed sidewall profile. The offset O may be in a range of 0.1 μm-20 μm.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.