Vertical semiconductor device with enhanced contact structure and associated methods
US11664427B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2022 |
| Grant date | May 30, 2023 |
| Priority date | — |
| Expiry date | May 23, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench. The superlattice layer may comprise stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer. Each at least one non-semiconductor monolayer of each group of layers may be constrained within a crystal lattice of adjacent base semiconductor portions. The vertical semiconductor device may also include a doped semiconductor layer adjacent the superlattice layer, and a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.