Multi-addressing mode for DMA and non-sequential read and write patterns

US11669464B1 · kind B1 · utility

Assignee

• XILINX, INC. · US

Inventors

• Goran H K Bilski · Mölndal, SE
• Baris Ozgul · Dublin, IE
• David Clarke · Dublin, IE
• Juan J. Noguera Serra · San Jose, US
• Jan Langer · Chemnitz, DE
• Zachary Blaise Dickman · Dublin, IE
• Sneha Bhalchandra Date · Santa Clara, US
• Tim Tuan · San Jose, US

Key dates

• Filing date: Apr 24, 2020
• Grant date: Jun 6, 2023
• Expiry date: Sep 10, 2040

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/1024
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Examples herein describe performing non-sequential DMA read and writes. Rather than storing data sequentially, a DMA engine can write data into memory using non-sequential memory addresses. A data processing engine (DPE) controller can submit a first job using first parameters that instruct the DMA engine to store data using a first non-sequential write pattern. The DPE controller can also submit a second job using second parameters that instruct the DMA engine to store data using a second, different non-sequential write pattern. In this manner, the DMA engine can switch to performing DMA writes using different non-sequential patterns. Similarly, the DMA engine can use non-sequential reads to retrieve data from memory. When performing a first DMA read, the DMA engine can retrieve data from memory using a first sequential pattern and then perform a second DMA read where data is retrieved from memory using a second non-sequential read pattern.