Patent · US Active

Automatic test pattern generation circuitry in multi power domain system on a chip

US11680982B2 · kind B2 · utility

0Cited by

1References

17Claims

0Family size

Assignee

STMicroelectronics International N.V. · NL

Inventors

Venkata Narayanan Srinivasan · Greater Noida, IN
Manish Sharma · Sunnyvale, US
Tripti Gupta · Noida, IN

Key dates

Filing date	Oct 26, 2021
Grant date	Jun 20, 2023
Priority date	—
Expiry date	Oct 26, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG06F1/18
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Described herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using a same scan chain compressor-decompressor circuit may be performed. Also disclosed herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using multiple different scan chain compressor-decompressor circuits may be performed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.