Input and digital output mechanisms for analog neural memory in a deep learning artificial neural network

US11683933B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Hieu Van Tran · San Jose, US
• Steven Lemke · Boulder Creek, US
• Vipin Tiwari · Dublin, US
• Nhan Do · Saratoga, US
• Mark Reiten · Alamo, US

Key dates

• Filing date: Dec 14, 2020
• Grant date: Jun 20, 2023
• Expiry date: Apr 11, 2041

Classification

• Technology area (CPC —): General

Abstract

Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input pulses applied to a terminal of the selected memory cell, further resulting in a series of output signals that are summed to determine the value stored in the selected memory cell. In another embodiment, an input comprises a set of input bits, where each input bit results in a single pulse or no pulse being applied to a terminal of the selected memory cell, further resulting in a series of output signals which are then weighted according to the binary bit location of the input bit, and where the weighted signals are then summed to determine the value stored in the selected memory cell.