Vias in composite IC chip structures

US11694986B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Adel A. Elsherbini · Chandler, US
• Patrick Morrow · Portland, US
• Johanna M. Swan · Scottsdale, US
• Shawna M. Liff · Scottsdale, US
• Mauro Kobrinksy · Portland, US
• Van H. Le · Portland, US
• Gerald Pasdast · San Jose, US

Key dates

• Filing date: Oct 13, 2021
• Grant date: Jul 4, 2023
• Expiry date: Oct 13, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/19105
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.