Circuit and method for scan testing

US11714131B1 · kind B1 · utility

Assignee

• STMicroelectronics International N.V. · NL

Inventors

• Venkata Narayanan Srinivasan · Greater Noida, IN
• Manish Sharma · Sunnyvale, US
• Shiv Kumar Vats · Greater Noida, IN
• Umesh Chandra Srivastava · Greater Noida, IN

Key dates

• Filing date: Mar 21, 2022
• Grant date: Aug 1, 2023
• Expiry date: Mar 21, 2042

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318594
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

In an embodiment, a method for performing scan testing includes: generating first and second scan clock signals; providing the first and second scan clock signals to first and second scan chains, respectively, where the first and second scan clock signals includes respective first shift pulses when a scan enable signal is asserted, and respective first capture pulses when the scan enable signal is deasserted, where the first shift pulse of the first and second scan clock signals correspond to a first clock pulse of a first clock signal, where the first capture pulse of the first scan clock signal corresponds to a second clock pulse of the first clock signal, and where the first capture pulse of the second scan clock signal corresponds to a first clock pulse of a second clock signal different from the first clock signal.