Fully molded semiconductor structure with through silicon via (TSV) vertical interconnects
US11728248B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2022 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Jun 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.