Memory system with dynamic calibration using a variable adjustment mechanism
US11733929B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2022 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Aug 15, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a processing device configured to iteratively update a center read level according to a first step size after reading a subset of memory cells according to a set of read levels including the center read level; track an update direction for the processing device to use when iteratively updating the center read level, wherein the update direction corresponds to an increase or a decrease in the center read level; detect a change condition based on updating the center read level according to the first step size; and iteratively update the center read level according to a second step size based on detection of the change condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.