Adjusting read-level thresholds based on write-to-write delay
US11742029B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2021 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Nov 11, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes performing a first write operation that writes data to a first memory unit of a group of memory units in a memory device, determining a write-to-write (W2W) delay based on a time difference between the first write operation and a second write operation on a memory unit in the group of memory units, wherein the second write operation occurred prior to the first write operation, identifying a threshold time criterion that is satisfied by the W2W delay, identifying a first read voltage level associated with the threshold time criterion, and associating the first read voltage level with a second memory unit of the group of memory units. The second memory unit can be associated with a second read voltage level that satisfies a selection criterion based on a comparison of the second read voltage level to the first read voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.