Wafer transport assembly with integrated buffers
US11764086B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2022 |
| Grant date | Sep 19, 2023 |
| Priority date | — |
| Expiry date | Jul 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67769
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate processing system configured to process substrates includes a substrate transport assembly that encloses a controlled environment defined within a continuous transport volume and at least two process modules coupled to the substrate transport assembly. The substrate transport assembly is configured to transport substrates to and from the at least two process modules through the continuous transport volume. At least two gas boxes are configured to deliver gas mixtures to the at least two process modules. An exhaust duct configured to selectively evacuate the at least two process modules through the at least two gas boxes. Surfaces of the at least two gas boxes include perforations configured to allow gases to flow from the at least two gas boxes into the exhaust duct.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.