Patent · US Active

Compensation for leakage in an array of analog neural memory cells in an artificial neural network

US11783904B2 · kind B2 · utility

0Cited by

6References

8Claims

0Family size

Assignee

Silicon Storage Technology, Inc. · US

Inventors

Hieu Van Tran · San Jose, US
Thuan Vu · San Jose, US
Stephen Trinh · San Jose, US
Stanley Hong · Palo Alto, US
Anh Ly · San Jose, US
Steven Lemke · Boulder Creek, US
Nha Thanh Nguyen · Shoreline, US
Vipin Tiwari · Dublin, US
Nhan Do · Saratoga, US

Key dates

Filing date	Jun 13, 2022
Grant date	Oct 10, 2023
Priority date	—
Expiry date	Jun 13, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/5006
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one example, a method is disclosed of compensating for leakage in an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bitline, the method comprising measuring leakage for a column of analog neural non-volatile memory cells coupled to a bitline; storing the measured leakage value; and applying the measured leakage value during a read operation of the column of analog neural non-volatile memory cells to compensate for the leakage.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.