Semiconductor structure and manufacturing method thereof
US11793091B2 · kind B2 · utility
1Cited by
3References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2020 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Jan 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.