Split-gate flash memory cell with improved control gate capacitive coupling, and method of making same

US11799005B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Leo Xing · Shanghai, CN
• Chunming Wang · Nanhu, CN
• Xian Liu · Sunnyvale, US
• Nhan Do · Saratoga, US
• Guo Xiang Song · Shanghai, CN

Key dates

• Filing date: Jun 14, 2021
• Grant date: Oct 24, 2023
• Expiry date: Jun 14, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A method of forming a memory device that includes forming a first insulation layer, a first conductive layer, and a second insulation layer on a semiconductor substrate, forming a trench in the second insulation layer to expose the upper surface of the first conductive layer, performing an oxidation process and a sloped etch process to reshape the upper surface to a concave shape, forming a third insulation layer on the reshaped upper surface, forming a conductive spacer on the third insulation layer, removing portions of the first conductive layer leaving a floating gate under the conductive spacer with the reshaped upper surface terminating at a side surface at a sharp edge, and forming a word line gate laterally adjacent to and insulated from the floating gate. The conductive spacer includes a lower surface that faces and matches the shape of the reshaped upper surface.