Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact

US11799009B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Biswajeet Guha · Hillsboro, US
• William Hsu · Hillsboro, US
• Chung-Hsun Lin · White Plains, US
• Kinyip Phoa · Beaverton, US
• Oleg Golonzka · Beaverton, US
• Tahir Ghani · Portland, US

Key dates

• Filing date: Dec 17, 2019
• Grant date: Oct 24, 2023
• Expiry date: Feb 21, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/834

Abstract

Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.