Method of fabrication thereof a multi-level vertical memory device including inter-level channel connector

US11805643B2 · kind B2 · utility

Assignee

• YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

• Ruo Fang Zhang · 红钢城街道, CN
• Enbo Wang · Hubei, CN
• Haohao Yang · 红钢城街道, CN
• Qianbing Xu · 红钢城街道, CN
• Yushi Hu · 红钢城街道, CN
• Qian Tao · Singapore, SG

Key dates

• Filing date: Aug 31, 2021
• Grant date: Oct 31, 2023
• Expiry date: Oct 22, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/27

Abstract

Aspects of the disclosure provide methods for manufacturing semiconductor devices. One of the methods forms a string of transistors in a semiconductor device over a substrate of the semiconductor device. The method includes forming a first substring of transistors having a first channel structure that includes a first channel layer and a first gate dielectric structure that extend along a vertical direction over the substrate. The method includes forming a channel connector over the first substring and forming the second substring above the channel connector. The second substring has a second channel structure. The second channel structure includes the second channel layer and a second gate dielectric structure that extend along the vertical direction. The second gate dielectric structure is formed above the channel connector. The channel connector electrically couples the first channel layer and the second channel layer.