Patent · US Active

Systems and methods for synchronization of multi-thread lanes

US11816500B2 · kind B2 · utility

0Cited by

5References

25Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Valentin Andrei · San Jose, US
Subramaniam Maiyuran · Citrus, US
SungYe Kim · Folsom, US
Varghese George · Folsom, US
Altug Koker · Cameron Park, US
Aravindh Anantaraman · Folsom, US

Key dates

Filing date	Mar 15, 2019
Grant date	Nov 14, 2023
Priority date	—
Expiry date	Aug 14, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG06T1/20
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Apparatuses to synchronize lanes that diverge or threads that drift are disclosed. In one embodiment, a graphics multiprocessor includes a queue having an initial state of groups with a first group having threads of first and second instruction types and a second group having threads of the first and second instruction types. A regroup engine (or regroup circuitry) regroups threads into a third group having threads of the first instruction type and a fourth group having threads of the second instruction type.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.