Valentin Andrei
38Patents
3h-index
48Co-inventors
55Inventor score
Filing activity: Mar 15, 2019 → Feb 5, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11620256B2 | Systems and methods for improving cache efficiency and utilization | Physics | 32 | Active |
| US11016929B2 | Scalar core integration | Physics | 6 | Active |
| US10909039B2 | Data prefetching for graphics data processing | Emerging Cross-Sectional Technologies | 3 | Active |
| US11409693B2 | Scalar core integration | Physics | 2 | Active |
| US11119820B2 | Local memory sharing between kernels | Emerging Cross-Sectional Technologies | 2 | Active |
| US11232533B2 | Memory prefetching in multiple GPU environment | Physics | 2 | Active |
| US11036545B2 | Graphics systems and methods for accelerating synchronization using fine grain dependency check and scheduling optimizations based on available shared memory space | Physics | 1 | Active |
| US11227358B2 | Systems and methods for exploiting queues and transitional storage for improved low-latency high-bandwidth on-die data retrieval | Physics | 1 | Active |
| US11762804B2 | Scalar core integration | Physics | 1 | Active |
| US12223353B2 | Systems and methods for synchronization of multi-thread lanes | Physics | 0 | Active |
| US11869113B2 | Systems and methods for exploiting queues and transitional storage for improved low-latency high-bandwidth on-die data retrieval | Physics | 0 | Active |
| US12099461B2 | Multi-tile memory management | Physics | 0 | Active |
| US12056059B2 | Systems and methods for cache optimization | Physics | 0 | Active |
| US11954062B2 | Dynamic memory reconfiguration | Physics | 0 | Active |
| US11816500B2 | Systems and methods for synchronization of multi-thread lanes | Physics | 0 | Active |
| US12293431B2 | Sparse optimizations for a matrix accelerator architecture | Physics | 0 | Active |
| US11934342B2 | Assistance for hardware prefetch in cache access | Physics | 0 | Active |
| US12182035B2 | Systems and methods for cache optimization | Physics | 0 | Active |
| US11409658B2 | Data prefetching for graphics data processing | Emerging Cross-Sectional Technologies | 0 | Active |
| US12066975B2 | Cache structure and utilization | Physics | 0 | Active |
| US12386779B2 | Dynamic memory reconfiguration | Physics | 0 | Active |
| US12141094B2 | Systolic disaggregation within a matrix accelerator architecture | Physics | 0 | Active |
| US11809905B2 | Local memory sharing between kernels | Emerging Cross-Sectional Technologies | 0 | Active |
| US12373912B2 | Prefetch status notification for memory prefetching | Physics | 0 | Active |
| US12117962B2 | Scalar core integration | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.