Tagged memory operated at lower vmin in error tolerant system
US11836346B2 · kind B2 · utility
0Cited by
9References
13Claims
0Family size
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Key dates
| Filing date | May 12, 2022 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | May 12, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.