Methods of patterning small features
US11837471B2 · kind B2 · utility
0Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2020 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | Jun 14, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device includes depositing a first layer over a substrate and patterning the first layer using an extreme ultraviolet (EUV) lithography process to form a patterned layer and expose portions of the substrate. The method includes, in a plasma processing chamber, generating a first plasma from a gas mixture including SiCl4 and one or more of argon, helium, nitrogen, and hydrogen. The method includes exposing the substrate to the first plasma to deposit a second layer including silicon over the patterned layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.