Semiconductor devices with package-level configurability
US11848323B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2021 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Sep 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.