Integrated circuit device structures and double-sided electrical testing

US11854894B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Valluri Rao · Saratoga, US
• Patrick Morrow · Portland, US
• Rishabh Mehandru · Portland, US
• Doug B. Ingerly · Portland, US
• Kimin Jun · Hillsboro, US
• Kevin P. O'Brien · Cincinnati, US
• Paul B. Fischer · Portland, US
• Szuya S. Liao · Portland, US
• Bruce A. Block · Portland, US

Key dates

• Filing date: Dec 4, 2020
• Grant date: Dec 26, 2023
• Expiry date: Dec 4, 2040

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02E10/50
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.