Patent · US Active

Method of forming a chip package and chip package

US11862600B2 · kind B2 · utility

1Cited by
1References
22Claims
0Family size

Assignee

Inventors

Key dates

Filing dateOct 1, 2021
Grant dateJan 2, 2024
Priority date
Expiry dateMar 23, 2042

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/15738
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A method of forming a chip package is provided. The method includes providing a malleable carrier with a layer of an electrically conductive material formed thereon, and positive fitting the malleable carrier to a chip to at least partially enclose the chip with the malleable carrier. The layer at least partially physically contacts the chip, such that the layer electrically contacts a chip contact of the chip. The layer forms a redistribution layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.