Controlling coarse pixel size from a stencil buffer

US11869119B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Karthik Vaidyanathan · San Francisco, US
• Prasoonkumar Surti · Folsom, US
• Hugues Labbe · Folsom, US
• Atsuo Kuwahara · Portland, US
• Sameer Kp · Bengaluru, IN
• Jonathan Kennedy · Bristol, GB
• Murali Ramadoss · Folsom, US
• Michael Apodaca · Folsom, US
• Abhishek Venkatesh · Hillsboro, US

Key dates

• Filing date: Feb 7, 2022
• Grant date: Jan 9, 2024
• Expiry date: Mar 14, 2042

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T2210/52
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.