Three-dimensional memory device including low-k drain-select-level isolation structures and methods of forming the same
US11871580B2 · kind B2 · utility
2Cited by
13References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 11, 2021 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Dec 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.