Non-volatile memory with engineered channel gradient
US11881271B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2022 |
| Grant date | Jan 23, 2024 |
| Priority date | — |
| Expiry date | Oct 8, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To save power during a read process, NAND strings of each sub-block of a block have independently controlled source side select lines connected to source side select gates and drain side select lines connected to drain side select gates so that NAND strings of unselected sub-blocks can float and not draw current. To prevent read disturb in NAND strings of unselected sub-blocks, after all word lines are raised to a pass gate voltage, unselected word lines nearby the selected word line are lowered to respective intermediate voltages while lowering the voltage on the selected word line in order to achieve a channel potential gradient in the floated NAND strings of the unselected sub-blocks that does not result in read disturb. Subsequently, the selected word line is raised to the appropriate read compare voltage so the selected memory cells can be sensed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.