Semiconductor device with a porous portion, wafer composite and method of manufacturing a semiconductor device
US11881397B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 20, 2022 |
| Grant date | Jan 23, 2024 |
| Priority date | — |
| Expiry date | Jul 20, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/668
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.