Select gate transistor with segmented channel fin
US11887667B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2021 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Jun 1, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells. The channel structures can be implemented as a segmented portion for drains and a portion opposite a gate. The segmented portion includes one or more fins and one or more non-conductive regions with both fins and non-conductive regions extending vertically from the portion opposite the gate. Variations of a border region for the portion opposite the gate with the segmented portion can include fanged regions extending from the fins into the portion opposite the gate or rounded border regions below the non-conductive regions. Such select gate transistors can be formed using a single photo mask process. Additional devices, systems, and methods are discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.