Utilizing data pattern effect to control read clock timing and bit line kick for read time reduction
US11887674B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2022 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Aug 10, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory apparatus and method of operation is provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings coupled to one of a plurality of bit lines and are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is configured to read each of the memory cells in a read operation. For each one of the memory cells, the control means is also configured to offset at least one of a bit line settling time and a kick voltage during the read operation based on a probability of at least one neighboring one of the plurality of bit lines being coupled to the memory cells retaining the threshold voltage corresponding to a different one of the plurality of data states than the one of the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.