Forming a sacrificial liner for dual channel devices
US11894462B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2021 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Oct 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.