Patent · US Active

Wafer-level test method for optoelectronic chips

US11906579B2 · kind B2 · utility

0Cited by

2References

6Claims

0Family size

Assignee

JENOPTIK GmbH · DE

Inventors

Tobias Gnausch · Östringen, DE
Armin Grundmann · Jena, DE
Thomas Kaden · Dresden, DE
Norik Janunts · Jena, DE
Robert BUETTNER · Jena, DE
Christian KARRAS · Jena, DE

Key dates

Filing date	Jun 19, 2020
Grant date	Feb 20, 2024
Priority date	—
Expiry date	Nov 3, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/2891
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A method for the testing of optoelectronic chips which are arranged on a wafer and have electrical interfaces in the form of contact pads and optical interfaces which are arranged to be fixed relative thereto in the form of optical deflection elements, e.g., grating couplers, with a specific coupling angle. The wafer is adjusted in three adjustment steps with one of the chips relative to a contacting module such that the electrical interfaces of the chip and contacting module contact one another, and the optical interfaces of the chip and contacting module occupy a maximum position of the optical coupling.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.