Managing an adjustable write-to-read delay based on cycle counts in a memory sub-system
US11914889B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Nov 30, 2022 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | Nov 30, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A current cycle count associated with a memory sub-system is determined. The current cycle count is compared to a set of cycle count threshold levels to determine a current lifecycle stage of the memory sub-system. A temperature associated with the memory sub-system is measured. The temperature is compared to a set of temperature levels to determine a current temperature level of the memory sub-system. A write-to-read delay time corresponding to the current lifecycle stage and the current temperature level is determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.