Memory devices with four data line bias levels
US11915758B2 · kind B2 · utility
0Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2023 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | Jan 10, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5671
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.