Variable bit line bias for nonvolatile memory
US11942157B2 · kind B2 · utility
2Cited by
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20Claims
0Family size
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Key dates
| Filing date | Mar 17, 2022 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Aug 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided that includes a word line coupled to a word line driver circuit, bit lines, a plurality of non-volatile memory cells each coupled to the word line and a corresponding one of the bit lines, and a control circuit coupled to the word line and the bit lines. The control circuit is configured to program the memory cells by causing the word line driver to apply a program pulse to the word line, and biasing each bit line to a corresponding bit line voltage that has a value that varies based on a distance between the word line driver and the corresponding bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.