Memory architecture with shared bitline at back-end-of-line

US11950407B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Juan G. Alzate Vinasco · Tigard, US
• Travis W. Lajoie · Forest Grove, US
• Abhishek A. Sharma · Hillsboro, US
• Kimberly Pierce · Beaverton, US
• Elliot N. Tan · Portland, US
• Yu-Jin Chen · Hillsboro, US
• Van H. Le · Portland, US
• Pei-Hua Wang · Beaverton, US
• Bernhard Sell · Dresden, DE

Key dates

• Filing date: Mar 24, 2020
• Grant date: Apr 2, 2024
• Expiry date: Aug 2, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/60
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.