Nano transistors with source/drain having side contacts to 2-D material

US11955527B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Chao-Ching Cheng · Hsinchu, TW
• Yi-Tse Hung · Hsinchu, TW
• Hung-Li Chiang · Taipei, TW
• Tzu-Chiang Chen · Hsinchu, TW
• Lain-Jong Li · Hsinchu, TW
• Jin Cai · Hubei, CN

Key dates

• Filing date: Jun 18, 2021
• Grant date: Apr 9, 2024
• Expiry date: Jan 16, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.