Method of forming memory cells, high voltage devices and logic devices on a semiconductor substrate
US11968829B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2022 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Sep 17, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method includes recessing an upper surface of a substrate in first and second areas relative to a third area, forming a first conductive layer in the first area, forming a second conductive layer in the three areas, selectively removing the first and second conductive layers in the first area, while maintaining the second conductive layer in the second and third areas, leaving pairs of stack structures in the first area respectively having a control gate of the second conductive layer and a floating gate of the first conductive layer, forming a third conductive layer in the three areas, recessing the upper surface of the third conductive layer below tops of the stack structures and removing the third conductive layer from the second and third areas, removing the second conductive layer from the second and third areas, and forming blocks of metal material in the second and third areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.