Hybrid binning
US11972518B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2020 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | Sep 25, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device and a method of tiled rendering of an image for display is provided. The processing device includes memory and a processor. The processor is configured to receive the image comprising one or more three dimensional (3D) objects, divide the image into tiles, execute coarse level tiling for the tiles of the image and execute fine level tiling for the tiles of the image. The processing device also includes same fixed function hardware used to execute the coarse level tiling and the fine level tiling. The processor is also configured to determine visibility information for a first one of the tiles. The visibility information is divided into draw call visibility information and triangle visibility information for each remaining tile of the image.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.