1D vertical edge blocking (VEB) via and plug

US11972979B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Leonard P. GULER · Hillsboro, US
• Michael K. Harper · Hillsboro, US
• Suzanne S. Rich · Hillsboro, US
• Charles H. Wallace · Portland, US
• Curtis W. Ward · Hillsboro, US
• Richard E. Schenker · Portland, US
• Paul A. Nyhus · Portland, US
• Mohit K. HARAN · Hillsboro, US
• Reken Patel · Portland, US
• Swaminathan Sivakumar · Portland, US

Key dates

• Filing date: Jun 7, 2023
• Grant date: Apr 30, 2024
• Expiry date: Jun 7, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.