Dynamic sense amplifier supply voltage for power and die size reduction
US11978516B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2022 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Nov 10, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06565
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system having a dynamic supply voltage to sense amplifiers. The supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.